{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T02:41:26Z","timestamp":1725763286459},"publisher-location":"Cham","reference-count":13,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783319038582"},{"type":"electronic","value":"9783319038599"}],"license":[{"start":{"date-parts":[[2013,1,1]],"date-time":"2013-01-01T00:00:00Z","timestamp":1356998400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2013,1,1]],"date-time":"2013-01-01T00:00:00Z","timestamp":1356998400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2013,1,1]],"date-time":"2013-01-01T00:00:00Z","timestamp":1356998400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013]]},"DOI":"10.1007\/978-3-319-03859-9_15","type":"book-chapter","created":{"date-parts":[[2013,12,9]],"date-time":"2013-12-09T12:54:34Z","timestamp":1386593674000},"page":"186-195","source":"Crossref","is-referenced-by-count":0,"title":["Unimodular Loop Transformations with Source-to-Source Translation for GPUs"],"prefix":"10.1007","author":[{"given":"Pasquale","family":"Cantiello","sequence":"first","affiliation":[]},{"given":"Beniamino","family":"Di Martino","sequence":"additional","affiliation":[]},{"given":"Francesco","family":"Piccolo","sequence":"additional","affiliation":[]}],"member":"297","reference":[{"key":"15_CR1","unstructured":"Amini, M., Ancourt, C., Coelho, F., Irigoin, F., Jouvelot, P., Keryell, R., Villalon, P., Creusillet, B., Guelton, S.: PIPS Is not (just) Polyhedral Software. In: International Workshop on Polyhedral Compilation Techniques (IMPACT 2011) (April 2011)"},{"key":"15_CR2","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"244","DOI":"10.1007\/978-3-642-11970-5_14","volume-title":"Compiler Construction","author":"M. Baskaran","year":"2010","unstructured":"Baskaran, M., Ramanujam, J., Sadayappan, P.: Automatic C-to-CUDA code generation for affine programs. In: Gupta, R. (ed.) CC 2010. LNCS, vol.\u00a06011, pp. 244\u2013263. Springer, Heidelberg (2010)"},{"key":"15_CR3","unstructured":"Cantiello, P., Di Martino, B.: Software porting support with component based and language neutral source code analysis. International Journal of Computational Science and Engineering (IJCSE) (to appear)"},{"key":"15_CR4","series-title":"Lecture Notes in Computer Science","doi-asserted-by":"publisher","first-page":"188","DOI":"10.1007\/978-3-642-29740-3_22","volume-title":"Euro-Par 2011: Parallel Processing Workshops","author":"P. Cantiello","year":"2012","unstructured":"Cantiello, P., Di Martino, B.: Automatic source code transformation for gpus based on program comprehension. In: Alexander, M., et al. (eds.) Euro-Par 2011, Part II. LNCS, vol.\u00a07156, pp. 188\u2013197. Springer, Heidelberg (2012)"},{"key":"15_CR5","doi-asserted-by":"crossref","unstructured":"Cantiello, P., Di Martino, B., Moscato, F.: Compilers, Techniques and Tools for Supporting Programming Heterogeneous Many\/Multicore Systems, pp. 31\u201350. John Wiley and Sons Inc. (2014)","DOI":"10.1002\/9781118640708.ch02"},{"key":"15_CR6","unstructured":"Dolbeau, R.: HMPP: A hybrid multi-core parallel. In: First Workshop on General Purpose Processing on Graphics Processing Units, pp. 1\u20135 (2007)"},{"issue":"1","key":"15_CR7","doi-asserted-by":"publisher","first-page":"78","DOI":"10.1109\/TPDS.2010.62","volume":"22","author":"T.D. Han","year":"2011","unstructured":"Han, T.D., Abdelrahman, T.S.: hicuda: High-level gpgpu programming. IEEE Trans. Parallel Distrib. Syst.\u00a022(1), 78\u201390 (2011)","journal-title":"IEEE Trans. Parallel Distrib. Syst."},{"key":"15_CR8","doi-asserted-by":"crossref","first-page":"51","DOI":"10.1145\/1735688.1735698","volume-title":"Proceedings of the 3rd Workshop on General-Purpose Computation on Graphics Processing Units, GPGPU 2010","author":"A. Leung","year":"2010","unstructured":"Leung, A., Vasilache, N., Meister, B., Baskaran, M., Wohlford, D., Bastoul, C., Lethin, R.: A mapping path for multi-gpgpu accelerated computers from a portable high level programming abstraction. In: Proceedings of the 3rd Workshop on General-Purpose Computation on Graphics Processing Units, GPGPU 2010, pp. 51\u201361. ACM Press, New York (2010)"},{"key":"15_CR9","unstructured":"NVIDIA. CUDA: Compute Unified Device Architecture., \n http:\/\/www.nvidia.com\/cuda\/"},{"key":"15_CR10","unstructured":"Quinlan, D.: ROSE Compiler project., \n http:\/\/www.rosecompiler.org\/"},{"key":"15_CR11","unstructured":"Torquati, M., Vanneschi, M., Amini, M., Guelton, S., Keryell, R., Lanore, V., Pasquier, F.-X., Barreteau, M., Barr\u00e8re, R., Petrisor, C.-T., Lenormand, \u00c9., Cantini, C., De Stefani, F.: An innovative compilation tool-chain for embedded multi-core architectures. In: Embedded World Conference (February 2012)"},{"issue":"4","key":"15_CR12","doi-asserted-by":"publisher","first-page":"452","DOI":"10.1109\/71.97902","volume":"2","author":"M.E. Wolf","year":"1991","unstructured":"Wolf, M.E., Lam, M.S.: A loop transformation theory and an algorithm to maximize parallelism. IEEE Trans. Parallel Distrib. Syst.\u00a02(4), 452\u2013471 (1991)","journal-title":"IEEE Trans. Parallel Distrib. Syst."},{"key":"15_CR13","doi-asserted-by":"crossref","first-page":"43","DOI":"10.1145\/1735688.1735697","volume-title":"Proceedings of the 3rd Workshop on General-Purpose Computation on Graphics Processing Units, GPGPU 2010","author":"M. Wolfe","year":"2010","unstructured":"Wolfe, M.: Implementing the pgi accelerator model. In: Proceedings of the 3rd Workshop on General-Purpose Computation on Graphics Processing Units, GPGPU 2010, pp. 43\u201350. ACM, New York (2010)"}],"container-title":["Lecture Notes in Computer Science","Algorithms and Architectures for Parallel Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-319-03859-9_15","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,1,28]],"date-time":"2023-01-28T04:27:22Z","timestamp":1674880042000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/978-3-319-03859-9_15"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013]]},"ISBN":["9783319038582","9783319038599"],"references-count":13,"URL":"https:\/\/doi.org\/10.1007\/978-3-319-03859-9_15","relation":{},"ISSN":["0302-9743","1611-3349"],"issn-type":[{"type":"print","value":"0302-9743"},{"type":"electronic","value":"1611-3349"}],"subject":[],"published":{"date-parts":[[2013]]}}}
