iBet uBet web content aggregator. Adding the entire web to your favor.
iBet uBet web content aggregator. Adding the entire web to your favor.



Link to original content: https://api.crossref.org/works/10.1007/978-3-030-49345-5_28
{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,11]],"date-time":"2024-09-11T21:58:06Z","timestamp":1726091886137},"publisher-location":"Cham","reference-count":13,"publisher":"Springer International Publishing","isbn-type":[{"type":"print","value":"9783030493448"},{"type":"electronic","value":"9783030493455"}],"license":[{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2020,8,1]],"date-time":"2020-08-01T00:00:00Z","timestamp":1596240000000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021]]},"DOI":"10.1007\/978-3-030-49345-5_28","type":"book-chapter","created":{"date-parts":[[2020,7,31]],"date-time":"2020-07-31T13:06:13Z","timestamp":1596200773000},"page":"266-276","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["Optimization of Application-Specific L1 Cache Translation Functions of the LEON3 Processor"],"prefix":"10.1007","author":[{"given":"Nam","family":"Ho","sequence":"first","affiliation":[]},{"given":"Paul","family":"Kaufmann","sequence":"additional","affiliation":[]},{"given":"Marco","family":"Platzner","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2020,8,1]]},"reference":[{"key":"28_CR1","unstructured":"Corporation, A.: Amdahl 470V\/6 Machine Reference Manual (1976)"},{"key":"28_CR2","unstructured":"Intel: Improving real-time performance by utilizing cache allocation technology. Technical report, Intel (2015)"},{"key":"28_CR3","unstructured":"Intel: Intel 64 and IA-32 architectures software developer\u2019s manual volume 3B: system programming guide, Part 2. Technical report, Intel (2015)"},{"key":"28_CR4","unstructured":"Kim, K.Y., Baek, W.: Quantifying the performance and energy efficiency of advanced cache indexing for gpgpu computing. Microprocessors and Microsystems (2016). \nhttp:\/\/www.sciencedirect.com\/science\/article\/pii\/S0141933116000053"},{"key":"28_CR5","doi-asserted-by":"crossref","unstructured":"Givargis, T.: Improved indexing for cache miss reduction in embedded systems. In: Proceedings Design Automation Conference (DAC), pp. 875\u2013880. IEEE (2003)","DOI":"10.1145\/775832.776052"},{"key":"28_CR6","unstructured":"Patel, K., Macii, E., Benini, L., Poncino, M.: Reducing cache misses by application-specific re-configurable indexing. In: Proceedings of the 2004 IEEE\/ACM International Conference on Computer-aided Design (ICCAD), pp. 125\u2013130. IEEE Computer Society (2004)"},{"key":"28_CR7","doi-asserted-by":"crossref","unstructured":"Vandierendonck, H., Manet, P., Legat, J.: Application-specific reconfigurable XOR-indexing to eliminate cache conflict misses. In: Proceedings Design, Automation and Test in Europe (DATE), pp. 1\u20136. IEEE (2006)","DOI":"10.1109\/DATE.2006.243736"},{"key":"28_CR8","doi-asserted-by":"crossref","unstructured":"Wang, B., Liu, Z., Wang, X., Yu, W.: Eliminating intra-warp conflict misses in GPU. In: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 689\u2013694. EDA Consortium (2015)","DOI":"10.7873\/DATE.2015.0322"},{"key":"28_CR9","doi-asserted-by":"crossref","unstructured":"Seznec, A., Bodin, F.: Skewed associative caches. Technical report 1655, INRIA (1992)","DOI":"10.1007\/3-540-56891-3_24"},{"key":"28_CR10","doi-asserted-by":"crossref","unstructured":"Diamond, J.R., Fussell, D.S., Keckler, S.W.: Arbitrary modulus indexing. In: Proceedings of the 47th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO), pp. 140\u2013152. IEEE Computer Society (2014)","DOI":"10.1109\/MICRO.2014.13"},{"key":"28_CR11","doi-asserted-by":"crossref","unstructured":"Kaufmann, P., Plessl, C., Platzner, M.: EvoCaches: Application-specific Adaptation of Cache Mappingsm, pp. 11\u201318. IEEE CS (2009)","DOI":"10.1109\/AHS.2009.26"},{"key":"28_CR12","unstructured":"Aeroflex Gaisler: Grlib. \nhttp:\/\/www.gaisler.com\/products\/grlib\/grlib.pdf"},{"key":"28_CR13","doi-asserted-by":"crossref","unstructured":"Ho, N., Kaufmann, P., Platzner, M.: A hardware\/software infrastructure for performance monitoring on LEON3 multicore platforms. In: Proceedings International Conference on Field Programmable Logic and Applications (FPL) (2014)","DOI":"10.1109\/FPL.2014.6927437"}],"container-title":["Advances in Intelligent Systems and Computing","Proceedings of the 11th International Conference on Soft Computing and Pattern Recognition (SoCPaR 2019)"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/978-3-030-49345-5_28","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,7,31]],"date-time":"2020-07-31T13:27:40Z","timestamp":1596202060000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/978-3-030-49345-5_28"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,8,1]]},"ISBN":["9783030493448","9783030493455"],"references-count":13,"URL":"https:\/\/doi.org\/10.1007\/978-3-030-49345-5_28","relation":{},"ISSN":["2194-5357","2194-5365"],"issn-type":[{"type":"print","value":"2194-5357"},{"type":"electronic","value":"2194-5365"}],"subject":[],"published":{"date-parts":[[2020,8,1]]},"assertion":[{"value":"1 August 2020","order":1,"name":"first_online","label":"First Online","group":{"name":"ChapterHistory","label":"Chapter History"}},{"value":"SoCPaR","order":1,"name":"conference_acronym","label":"Conference Acronym","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"International Conference on Soft Computing and Pattern Recognition","order":2,"name":"conference_name","label":"Conference Name","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"Hyderabad","order":3,"name":"conference_city","label":"Conference City","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"India","order":4,"name":"conference_country","label":"Conference Country","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"2019","order":5,"name":"conference_year","label":"Conference Year","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"13 December 2019","order":7,"name":"conference_start_date","label":"Conference Start Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"15 December 2019","order":8,"name":"conference_end_date","label":"Conference End Date","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"11","order":9,"name":"conference_number","label":"Conference Number","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"socpar2019","order":10,"name":"conference_id","label":"Conference ID","group":{"name":"ConferenceInfo","label":"Conference Information"}},{"value":"http:\/\/www.mirlabs.net\/socpar19\/","order":11,"name":"conference_url","label":"Conference URL","group":{"name":"ConferenceInfo","label":"Conference Information"}}]}}