{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,8,11]],"date-time":"2024-08-11T05:53:10Z","timestamp":1723355590326},"reference-count":38,"publisher":"Wiley","issue":"10","license":[{"start":{"date-parts":[[2023,6,1]],"date-time":"2023-06-01T00:00:00Z","timestamp":1685577600000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/onlinelibrary.wiley.com\/termsAndConditions#vor"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61974087"],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["onlinelibrary.wiley.com"],"crossmark-restriction":true},"short-container-title":["Circuit Theory & Apps"],"published-print":{"date-parts":[[2023,10]]},"abstract":"Summary<\/jats:title>Operational amplifier (Op Amp) is a special class of analog integrated circuits. Multiple\u2010stage Op Amp design is of particular interest recently. However, analysis of this class of circuits has to be done manually and requires advanced skills. Automatic analysis of this class of circuits is studied in this paper, which takes a novel approach by circuit recognition and symbolic generation. Circuit recognition is deterministic, implemented by deterministic circuit partitioning and functional block extraction methods. Symbolic analysis of extracted circuit blocks can subsequently be performed with greatly reduced complexity while generated models and equations bear more useful information for circuit design. Symbolic results so generated can be applied in design space exploration, including tasks like finding the limitation in circuit topology, conducting initial sizing, and determining performance tradeoffs. This paper proposes the key algorithms for realizing the recognition of a few well\u2010known functional blocks frequently used in CMOS Op Amp circuits and further explores the possibility of using the recognized circuit cells in combination with the gm\/ID method for circuit sizing. Preliminary tests show that this approach is a potential candidate for locating the performance boundaries of multiple\u2010stage Op Amps.<\/jats:p>","DOI":"10.1002\/cta.3673","type":"journal-article","created":{"date-parts":[[2023,6,2]],"date-time":"2023-06-02T02:00:20Z","timestamp":1685671220000},"page":"4521-4549","update-policy":"http:\/\/dx.doi.org\/10.1002\/crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Automatic generation of macromodels and design equations for application to Op Amp design"],"prefix":"10.1002","volume":"51","author":[{"ORCID":"http:\/\/orcid.org\/0000-0002-8655-3487","authenticated-orcid":false,"given":"Guoyong","family":"Shi","sequence":"first","affiliation":[{"name":"Department of Micro\/Nano\u2010electronics, School of Electronic, Information, and Electrical Engineering Shanghai Jiao Tong University Shanghai China"}]}],"member":"311","published-online":{"date-parts":[[2023,6]]},"reference":[{"key":"e_1_2_9_2_1","volume-title":"Symbolic Approximation and Modeling Techniques for Analysis and Design of Analog Circuits","author":"Hennig E","year":"2000"},{"key":"e_1_2_9_3_1","doi-asserted-by":"publisher","DOI":"10.2174\/97816080509561120101"},{"key":"e_1_2_9_4_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2006143"},{"key":"e_1_2_9_5_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2022.04.006"},{"key":"e_1_2_9_6_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2017.08.005"},{"key":"e_1_2_9_7_1","volume-title":"Symbolic Network Analysis","author":"Lin PM","year":"1991"},{"key":"e_1_2_9_8_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-3962-9"},{"key":"e_1_2_9_9_1","volume-title":"Symbolic Analysis and Reduction of VLSI Circuits","author":"Cheng CK","year":"2005"},{"key":"e_1_2_9_10_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4939-1103-5"},{"key":"e_1_2_9_11_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2229070"},{"key":"e_1_2_9_12_1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2619677"},{"key":"e_1_2_9_13_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2664065"},{"key":"e_1_2_9_14_1","doi-asserted-by":"publisher","DOI":"10.1145\/3015782"},{"key":"e_1_2_9_15_1","doi-asserted-by":"publisher","DOI":"10.1145\/3363499"},{"key":"e_1_2_9_16_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.535416"},{"key":"e_1_2_9_17_1","doi-asserted-by":"publisher","DOI":"10.1109\/4.597291"},{"key":"e_1_2_9_18_1","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-47101-3"},{"key":"e_1_2_9_19_1","doi-asserted-by":"publisher","DOI":"10.1587\/transele.E94.C.334"},{"key":"e_1_2_9_20_1","doi-asserted-by":"publisher","DOI":"10.1017\/9781108125840"},{"key":"e_1_2_9_21_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2018.02.002"},{"key":"e_1_2_9_22_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.3036683"},{"key":"e_1_2_9_23_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2021.03.003"},{"key":"e_1_2_9_24_1","doi-asserted-by":"crossref","unstructured":"McConaghyT PalmersP GielenG SteyaertM.Simultaneous multi\u2010topology multi\u2010objective sizing across thousands of analog circuit topologies. In: Proc. Design Automation Conference (DAC);2007:944\u2010947.","DOI":"10.1145\/1278480.1278712"},{"key":"e_1_2_9_25_1","doi-asserted-by":"crossref","unstructured":"McConaghyT PalmersP GielenG SteyaertM.Automated extraction of expert knowledge in analog topology selection and sizing. In: Proc. IEEE\/ACM Int'l Conference on Computer\u2010Aided Design (ICCAD);2008:392\u2010395.","DOI":"10.1109\/ICCAD.2008.4681603"},{"key":"e_1_2_9_26_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3153437"},{"key":"e_1_2_9_27_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3101691"},{"key":"e_1_2_9_28_1","doi-asserted-by":"publisher","DOI":"10.1145\/3522738"},{"key":"e_1_2_9_29_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2411796"},{"key":"e_1_2_9_30_1","doi-asserted-by":"publisher","DOI":"10.3390\/electronics8111268"},{"key":"e_1_2_9_31_1","doi-asserted-by":"publisher","DOI":"10.1002\/cta.2723"},{"key":"e_1_2_9_32_1","doi-asserted-by":"publisher","DOI":"10.1109\/81.376869"},{"key":"e_1_2_9_33_1","doi-asserted-by":"publisher","DOI":"10.1109\/81.557376"},{"key":"e_1_2_9_34_1","doi-asserted-by":"publisher","DOI":"10.1109\/81.948432"},{"key":"e_1_2_9_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2003.811437"},{"key":"e_1_2_9_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2007.900170"},{"key":"e_1_2_9_37_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2573920"},{"key":"e_1_2_9_38_1","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-019-01555-2"},{"key":"e_1_2_9_39_1","doi-asserted-by":"crossref","unstructured":"XieQ LiZ ShiG.Design space exploration of multi\u2010stage op amps by symbolic modeling and gm\/ID sampling. In: Proc IEEE International Symposium on EDA (ISEDA);2023:1\u20106. to appear.","DOI":"10.1109\/ISEDA59274.2023.10218716"}],"container-title":["International Journal of Circuit Theory and Applications"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/pdf\/10.1002\/cta.3673","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,12]],"date-time":"2023-10-12T02:19:46Z","timestamp":1697077186000},"score":1,"resource":{"primary":{"URL":"https:\/\/onlinelibrary.wiley.com\/doi\/10.1002\/cta.3673"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,6]]},"references-count":38,"journal-issue":{"issue":"10","published-print":{"date-parts":[[2023,10]]}},"alternative-id":["10.1002\/cta.3673"],"URL":"http:\/\/dx.doi.org\/10.1002\/cta.3673","archive":["Portico"],"relation":{},"ISSN":["0098-9886","1097-007X"],"issn-type":[{"value":"0098-9886","type":"print"},{"value":"1097-007X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,6]]},"assertion":[{"value":"2023-02-23","order":0,"name":"received","label":"Received","group":{"name":"publication_history","label":"Publication History"}},{"value":"2023-05-12","order":1,"name":"accepted","label":"Accepted","group":{"name":"publication_history","label":"Publication History"}},{"value":"2023-06-01","order":2,"name":"published","label":"Published","group":{"name":"publication_history","label":"Publication History"}}]}}
