Andrew Mcbride

Piggybacking Of Ecc Corrections Behind Loads

Application

#7043679 May 9, 2006

Filed

Jun 27, 2002

Inventor

Chetana N. Keltcher (Sunnyvale, CA) · William Alexander Hughes (Burlingame, CA) · Andrew McBride (Austin, TX)

Appl. No.

10/180207

Assignee

Advanced Micro Devices, Inc. (Sunnyvale, CA)

International Classification

G11C 29/00

U.S. Classification

714763, 714703, 714 52

Abstract

An apparatus including circuitry configured to detect and correct an ECC error in a non-targeted portion of a load access to a first data in a memory. An ECC error check circuit is configured to...

Branch Selector Prediction

Application

#5954816 Sep 21, 1999

Filed

Nov 19, 1997

Inventor

Thang M. Tran (Austin, TX) · David E. Kroesche (Pflugerville, TX) · Karthikeyan Muthusamy (Austin, TX) · Andrew McBride (Austin, TX)

Appl. No.

8/972988

Assignee

Advanced Micro Devices, Inc. (Sunnyvale, CA)

International Classification

G06F 938

U.S. Classification

712239

Abstract

A branch prediction unit includes a branch prediction entry corresponding to a group of contiguous instruction bytes. The branch prediction entry stores branch predictions corresponding to branch...

Apparatus For Managing System Interrupt Operations In A Computing System

Application

#5404457 Apr 4, 1995

Filed

Feb 14, 1992

Inventor

Douglas D. Gephardt (Austin, TX) · Andrew McBride (Austin, TX)

Appl. No.

7/837233

Assignee

Advanced Micro Devices, Inc. (Sunnyvale, CA)

International Classification

G06F 946

U.S. Classification

395325

Abstract

An apparatus for managing system interrupt operations in a computing system including a processing unit and peripheral devices. The apparatus comprises a transmission circuit for transmitting signals ...

User-Prioritized Cache Replacement

Application

#6349365 Feb 19, 2002

Filed

Oct 8, 1999

Inventor

Andrew McBride (Austin, TX)

Appl. No.

09/415892

Assignee

Advanced Micro Devices, Inc. (Sunnyvale, CA)

International Classification

G06F 1200

U.S. Classification

711133

Abstract

A method and apparatus for encoding cache replacement priority information is disclosed. A computer software program may be used to allow programmers to specify which portions of source or object...

Claim

What is claimed is: 1. A microprocessor comprising: a cache comprising a plurality of cache line storage locations and a corresponding plurality of replacement priority storage locations; a predecode ...

Reduced Size Storage Apparatus For Storing Cache-Line-Related Data In A High Frequency Microprocessor

Application

#6016545 Jan 18, 2000

Filed

Dec 16, 1997

Inventor

Rupaka Mahalingaiah (Austin, TX) · Andrew McBride (Austin, TX) · Thang M. Tran (Austin, TX)

Appl. No.

8/991694

Assignee

Advanced Micro Devices, Inc. (Sunnyvale, CA)

International Classification

G06F 938

U.S. Classification

712238

Abstract

A microprocessor stores cache-line-related data (e. g. branch predictions or predecode data, in the illustrated embodiments) in a storage which includes fewer storage locations than the number of...

Predecoding Technique For Indicating Locations Of Opcode Bytes In Variable Byte-Length Instructions Within A Superscalar Microprocessor

Application

#6049863 Apr 11, 2000

Filed

Jun 11, 1997

Inventor

Thang M. Tran (Austin, TX) · Rammohan Narayan (Austin, TX) · Andrew McBride (Austin, TX) · Karthikeyan Muthusamy (Austin, TX)

Appl. No.

8/873344

Assignee

Advanced Micro Devices, Inc. (Sunnyvale, CA)

International Classification

G06F 930

U.S. Classification

712213

Abstract

A predecode unit is configured to predecode variable byte-length instructions prior to their storage within an instruction cache of a superscalar microprocessor. The predecode unit generates three...