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Link to original content: http://github.com/riscv-boom/riscv-boom/issues
Issues · riscv-boom/riscv-boom · GitHub
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106 Open 191 Closed
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Issues list

mcause doesn't behave the same way on boom and spike
#713 opened Nov 14, 2024 by 90ICEDA
1
Differences in performance of the lhu command on boom and spike
#712 opened Nov 13, 2024 by 90ICEDA
Spike and boom's csr registers behave differently
#711 opened Nov 11, 2024 by 90ICEDA
Novel Contention-based Side Channel in Boom
#710 opened Nov 9, 2024 by zhangkanqi
4
Hardware breakpoint cannot resume execution
#709 opened Oct 15, 2024 by rxss11
Managing CSRs in BOOM
#704 opened Sep 15, 2024 by HakamAtassi
2
Improper Handling of Execute-Only Memory Regions in PMP Configuration on BOOM Core
#703 opened Aug 29, 2024 by riscv914
LoopPredictor can flip the prediction for branches immediately preceding the loop end
#702 opened Aug 25, 2024 by AlviseDeFaveri
[Bug Report] Leak secret data through delayed instruction fetching
#701 opened Aug 5, 2024 by Phantom1003
1
[Bug Report] Leak secret data through Speculative RSB Injection
#700 opened Aug 5, 2024 by Phantom1003
1
[Bug Report] Leak secret data through Speculative BTB Injection
#699 opened Aug 5, 2024 by Phantom1003
1
Load address misaligned exception can cause the meltdown attack on Boom v3.
#698 opened Jul 28, 2024 by Cpider
3
The FCSR register value setting problem in V-U mode causes inconsistent floating-point operation results
#694 opened Jun 18, 2024 by vincen-dev
fflags.NV is not update after fdiv.s instruction
#692 opened May 29, 2024 by zhangkanqi
Dual boom core simulation hang
#690 opened May 8, 2024 by crsullivan13
14
About the Load Queue design in Boom
#689 opened Apr 23, 2024 by zhaoxiahust
5
The error occurred during testing of boom core
#688 opened Apr 23, 2024 by hanyjie
6
Quad RV32 LargeBoomCore Config failed to boot core2/3 with wfi dead loop
#684 opened Mar 17, 2024 by zqf1995
RV32IF/IMF Support Request
#682 opened Mar 11, 2024 by pulkitgupta1217
2
Question about short-forward branch in frontend
#679 opened Jan 26, 2024 by Jerry-Tianchen
Executing Single-Precision Floating-Point with an invalid rm field does not throw the exception
#675 opened Jan 3, 2024 by morecoding2
1
fcsr 'invalid operation' flag is not set after fsqrt.s opreation
#674 opened Jan 2, 2024 by zhangkanqi
4
issue about ocelot RTL generate
#672 opened Dec 21, 2023 by menglinhan
Potential Bug at DCache WriteArb
#667 opened Nov 18, 2023 by Jerry-Tianchen
3
bug report: A core with prefetcher will trigger a page fault when starting kernel.
#666 opened Nov 15, 2023 by fangjiangff
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