8085 MICROPROCESSOR: PROGRAMMING AND INTERFACINGThis up-to-date and contemporary book is designed as a first level undergraduate text on micro-processors for the students of engineering (computer science, electrical, electronics, telecommunication, instrumentation), computer applications and information technology. It gives a clear exposition of the architecture, programming and interfacing and applications of 8085 microprocessor. Besides, it provides a brief introduction to 8086 and 8088 Intel microprocessors. The book focusses on : microprocessors starting from 4004 to 80586. instruction set of 8085 microprocessor giving the clear picture of the operations at the machine level. the various steps of the assembly language program development cycle. the hardware architecture of microcomputer built with the 8085 microprocessor. the role of the hardware interfaces: memory, input/output and interrupt, in relation to overall microcomputer system operation. peripheral chips such as 8255, 8253, 8259, 8257 and 8279 to interface with 8085 microprocessor and to program it for different applications. |
Contents
MICROPROCESSOR 2549 | 25 |
Generation of Wait Signal | 31 |
Serial InputOutput Signals | 37 |
Exercises | 48 |
Instruction | 55 |
Introduction | 122 |
SEMICONDUCTOR MEMORY | 153 |
PROGRAMMABLE PERIPHERAL INTERFACE 8255A 187205 | 187 |
Interrupt Sequence | 228 |
Interface of 8259A to 8085 Microprocessor | 238 |
SERIAL DATA TRANSFER 256271 | 256 |
PROGRAMMABLE KEYBOARDDISPLAY | 272 |
Solved Problems | 296 |
Maximum Mode Pins | 305 |
Bus Read Machine | 311 |
Exercises | 317 |
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Common terms and phrases
16 bits 8-bit data 8085 microprocessor accumulator active low address bus address lines addressing mode Arithmetic Logic Unit BDB T4 block diagram chip circuit clock Command Word contents control logic control signals control word counter data bus Data Bus Buffer data transfer decoder digit display RAM DMA cycle enables EPROMs execution fetch FIFO function HLDA I/O device incremented INTA interface interrupt acknowledge interrupt request INTR IO/M keyboard latch loaded machine cycle Macro RTL mask maximum mode memory location Micro mnemonic opcode Operand operation code OPFMC output Pin Configuration port Port-A processor pulse queue RD WR Read Only Memory Read/Write register pair reset Rotate scan segment register selected serial data shown in Fig single byte instruction stack pointer status register stored strobed subroutine SYNC character synchronous transmitter USART Write zero